(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a bipolar transistor device, featuring a three dimensional trench emitter region.
(2) Description of Prior Art
Although complimentary metal oxide semiconductor, (CMOS), devices have been extensively used to fabricate integrated circuits, bipolar devices, exhibiting faster switching speeds than CMOS devices, are now being used to increase the performance of bipolar-CMOS, (BiCMOS), designs, when compared to counterpart designs entailing only CMOS devices. In addition advances in bipolar configurations, such as emitter regions obtained from diffusion from overlying polysilicon emitter structures, compared to conventional emitter regions, obtained via ion implantation, directly into the semiconductor substrate, have allowed improved bipolar devices to be realized. For example the depth of emitter regions, formed from polysilicon emitter structures, can be maintained at narrower levels than emitter regions obtained via direct ion implantation procedures. This is a result of the absence of ion implantation channelling, and as a result of the elimination of a post-ion implant anneal, sometimes resulting in excessive drive-in of the emitter, into the base region. Therefore the use of the more controllable polysilicon emitter structure, has allowed the attainment of narrower base widths, which in results in higher performing bipolar device, in terms of frequency response, (Ft).
The emitter resistance is in part, a function of the level of interface area between the emitter, and underlying base region. However increasing the interface area directly increases the dimensions of the bipolar device, adversely influencing the objective of device miniaturization. This invention will describe the fabrication of a bipolar device, featuring a trench, polysilicon emitter structure, maximizing interface area while minimizing device area. In addition this invention will describe a novel procedure used to fabricate a narrow base region, along the sides of the emitter trench region. Prior art, such as Chambers et al, in U.S. Pat. No. 5,488,003, as well as Chambers et al, in U.S. No. 5,856,697, describe procedures used to create polysilicon emitter structures, located in a trench, however these prior arts do not teach the novel procedure described in this present invention, of forming narrow base widths, along the sides of the emitter trench, prior to the polysilicon filling of the emitter trench.